SCI Journals
J. Kim, Y. Lim, H. Yoon, Y. Lee, Y. Cho, T. Seong, and J. Choi, “An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators,” IEEE Journal of Solid-State Circuits (JSSC), Dec. 2019, invited from IEEE 2019 International Solid-State Circuits Conference (ISSCC).
H. Yoon, S. Park, and J. Choi, “A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally-Controlled Oscillators and Time-Interleaved Calibration,” IEEE Journal of Solid-State Circuits (JSSC), Feb. 2019
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi, “A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers”, IEEE Journal of Solid-State Circuits (JSSC), Feb. 2018.
H. Yoon, Y. Lee, Y. Lim, G. Tak, H. Kim, Y. Ho, and J. Choi, “A 0.56 – 2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2 – 4G Multi-Standard Cellular Transceivers”, IEEE Journal of Solid-State Circuits (JSSC), Mar. 2016.
H. Yoon, Y. Lee, and J. Choi, “A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core” IEEE Trans. Circuits Syst. II (TCAS-II), May 2014.
International Conferences
S. Yoo*, S. Park*, S. Choi*, Y. Cho, H. Yoon, C. Hwang, J. Choi, “An 82fsRMS-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector in 65nm CMOS,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2021. (* Equally-Credited Authors)
Y. Lim*, J. Kim*, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon, and J. Choi, “A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2020. (* Equally-Credited Authors)
J. Kim*, H. Yoon*, Y. Lim*, Y. Lee, Y. Cho, T. Seong, and J. Choi, “A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2019. (* Equally-Credited Authors)
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi, “Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2018.
S Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi, “Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers”, 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018.
S. Park, H. Yoon, and J. Choi, “An Ultra-Low Phase Noise All-Digital Multi-Frequency Generator Using Injection-Locked DCOs and Time-Interleaved Calibration,” IEEE Asian Solid-State Circuits (ASSCC), Nov. 2017.
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi, “A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600μW Frequency-Tracking Loop for mm-Band 5G Transceivers,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2017.
Y. Lee, H. Yoon, M. Kim, and J. Choi, “A PVT-Robust Low Reference Spur Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop,” IEEE VLSI Symposium, Jun. 2016.
Patents
A. Li, Y. Chao, D. Park, H. Yoon, T. O’sullivan, J. Yu, and Y. Tang, Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection, Filed in US, 2021
J. Choi, H. Yoon, and Y. Lee, Apparatus for High Frequency Division and the Calibration Logic for Correcting Divider’s Operation, Patent No.:10-2287-5150000, Aug. 03, 2021. (Granted)
J. Choi, H. Yoon, S. Park, and J. Kim, Frequency Discriminator Based on Delay Locked Loop, Patent No.:10-2056-5360000, Dec. 10, 2019. (Granted)
J. Choi, H. Yoon, and S. Park, Injection-Locked Multi-Clock-Frequency Generator Using a Time-Interleaved Multi-DCO Calibrator, Patent No.:10-1852832, Apr. 23, 2018. (Granted)
J. Choi, Y. Lee, and H. Yoon, A Low-Reference-Spur and Low-Jitter Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop with High Calibrating Precision, Application No.:10-2017-0008449, Jan. 18, 2017. (Filed)
J. Choi, J. Lee, and H. Yoon, Phase Generator Based on Delay Lock Loop Circuit and Delay Locking, Patent No.:10-1628160, Jun. 01, 2016 (Granted)
J. Choi, Y. Lee, and H. Yoon, PVT Calibrating Circuit and Method for Injection-Locked Ring-Oscillators, Patent No.:10-1548256, Aug. 24, 2015. (Granted)
J. Choi, and H. Yoon, Wideband LC-VCO Using a Transconductance-switching Technique, Patent No.: 10-1527291, Jun. 2, 2015. (Granted)